NAME
  qflow - Open-Source Digital Synthesis Flow

SYNOPSIS
  qflow [processes] [options] <module_name>

DESCRIPTION
 This is the main executable for a complete tool chain
 for synthesizing digital circuits starting
 from verilog source and ending in physical layout for a specific target
 fabrication process. In the world of commercial electronics, digital
 synthesis with a target application of a chip design is usually bundled
 into large EDA software systems. As commercial electronics designers need
 to maintain cutting-edge performance, these commercial toolchains get more
 and more expensive, and have largely priced themselves out of all but the
 established integrated circuit manufacturers. This leaves an unfortunate
 gap where startup companies and small businesses cannot afford to do any
 sort of integrated circuit design.
  
 Qflow tries to fill this gap.
  
PROCESSES
 synthesize         Synthesize verilog source
 place              Run initial placement
 sta                Static timing analysis
 route              Run placement and route
 decongest          Run congestion analysis, final place and route
 clean              Remove temporary working files
 display            Display routed result
 
 build              Run scripts synthesize to route
 all                Run scripts synthesize to display

OPTIONS
  -T, --tech <name>           Use technology <name>
  -p, --project <name>       Project root directory is <name>




AUTHOR
  This manual page was written by Ruben Undheim <ruben.undheim@gmail.com> for the Debian project (and may be used by others).
